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Chapter 17

IBM 650 instruction logic1

John W Carr III

The basic IBM 650 is a magnetic drum (10,0,0)2 decimal computer with one-plus-one address instruction logic. It has a storage of 1000 or 2000 10-digit words (plus sign) with addresses 0000-0999 or 0000-1999. More extended versions of the equipment have built-in floating point arithmetic and index accumulators, but the basic machine will be described here. There are three arithmetic registers in addition to the standard program register and program counter. All information from the drum to the arithmetic unit passes through a signed 10-digit distributor. A twenty-digit accumulator is divided into a lower and upper part, each of 10 digits with sign. Each of these is addressable (distributor 8001, lower accumulator 8002, and upper accumulator 8003). Each accumulator may be cleared to zero separately (in IBM 650 terminology, "reset"). The entire 20-digit register can be considered as a unit, or each part separately (but affecting the other in case of carries). The 10-digit instruction is broken down into the following form:

10

9

8

7

6

5

4

2

3

1

0

Op. Code

Data Address

Next Instruction Address

Sign

One particular instruction, Table Look-Up, allows automatic table search for one particular element in a table, which can be stored with a corresponding functional value. Input-output is via 80-digit numerical punched cards. An "alphabetic device" allows limited alphabetical entry on cards. Only certain 10-word groups on the magnetic drum are available for input and output. The following information is taken from an IBM 650 manual [Type 650, Magnetic Drum Data-Processing Machine Manual of Operations]. Much of the input-output is handled via board wiring, which is not described in detail below. The two-digit pair represents the machine code. The BRD (Branch on Digit) operation is used with special board wiring to tell when certain specific card punches exist.

Input-output instructions

70 RD (Read). This operation code causes the machine to read cards by a two-step process. First, the contents of the 10 words of read buffer storage are automatically transferred to one of the 20 (or 40) possible 10-word groups of read general storage. The group selected is determined by the D address of the Read instruction. Secondly, a card is moved under the reading brushes, and the information read is entered into buffer storage for the next Read instruction.

71 PCH (Punch). This operation code causes card punching in two steps. First the contents of one of the 20 (or 40) possible 10-word groups of punch storage are transferred to punch buffer storage. The group selected is specified by the D address of the Punch instruction. Secondly, the card is punched with the information from buffer storage.

69 LD (Load Distributor). This operation code causes the contents of the D address location of the instruction to be placed in the distributor.

24 STD (Store Distributor). This operation code causes the contents of the distributor with the distributor sign to be stored in the location specified by the D address of the instruction. The contents of the distributor remain undisturbed.

Addition and subtraction instructions

10 AU (Add to Upper). This operation code causes the contents of the D address location to be added to the contents of the upper half of the accumulator. The lower half of the accumulator will remain unaffected unless the addition causes the sign of the accumulator to change, in which case the contents of the lower half of the accumulator will be complemented. Also, the units position of the upper half of the accumulator will be reduced by one.

15 AL (Add to Lower). This operation code causes the contents of the D address location to be added to the contents of the lower half of the accumulator. The contents of the upper half of the accumulator could be affected by carries.

11 SU (Subtract from Upper). This operation code causes the contents of the D address location to be subtracted from the

1In E. M. Crabbe, S. Ramo, and D. E. Wooldridge (eds.), "Handbook of Automation, Computation, and Control," vol. 2, chap. 2, pp. 93-98, John Wiley & Sons, Inc., New York, 1959.
2Carr's triplet notation for: fractional significant digits, digits in exponent, and digits to left of radix point.

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